AIE-PL Subsystem Simulation Without CIPS - 2024.1 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
Release Date
2024-05-30
Version
2024.1 English

Often the hardware design comprising the platform hardware is co-developed with Vitis AI Engine graphs and PL kernels, possibly by different teams. Hardware Emulation of the full design with CIPS, AI Engine, and PL logic is not be preferred at the initial stage of the design, the simulation of only AI Engine with PL logic can help to simulate the subsystem faster. The AIE-PL Subsystem Simulation Without CIPS functionality enables users to simulate the design without CIPS block and enables focused simulation on subsystem (AI Engine with PL logic). The subsystem simulation can be run with XSIM or any supported third party simulator.

The Vitis Export flow enabled by v++ --link --export_archive performs standard linking design modifications, but stops before running Vivado synthesis and instead encapsulates all relevant design data (BD, IP repository) and XCLBIN metadata for the Xilinx Runtime (XRT) into a Vitis Metadata Archive (.vma) file, forgoing the normal automated Vivado simulation.

At the design level, the v++ command operates entirely within a dynamic region block design container (BDC) in the extensible hardware platform. Based on source input files, the v++ linker instantiates user-defined PL kernels, configures platform IP such as AI Engine, NoC, and soft interconnects, adds required design IP for AXI buses, clock domain crossing, data width conversion, and FIFO buffering, adds networks for hardware debugging, trace, and clocking, and creates connections between IP within the dynamic region.

The .vma file is imported into the original extensible platform project in the Vivado Design Suite using the vitis::import_archive Tcl procedure. The .vma IP repository is added to the Vivado project's IP repository and a new active variant for the dynamic region BDC is created. Development can then continue in the Vivado project, including additional design modifications, simulation, synthesis, and implementation.

The Vitis Export flow is mainly used to make modifications to the platform in Vivado after importing the .vma file. After modifications are completed, design(vma)can be taken to simulation by creating Test Bench or by adding Simulation sources to Vivado project. Simulation can be launched either using Vivado launch_simulation or export_simulation command.