Zynq UltraScale+ RFSoC XCZU49DR Configuration - Zynq UltraScale+ RFSoC XCZU49DR Configuration - UG1390

ZCU216 Evaluation Board User Guide (UG1390)
Document ID
UG1390
Release Date
2023-12-07
Revision
1.2 English

Zynq UltraScale+ RFSoC ZU49DR uses a multi-stage boot process documented in the Boot and Configuration chapter of the Zynq UltraScale+ Device Technical Reference Manual (UG1085).

Switch SW2 configuration option settings are identified in the following table.

Table 1. Mode Switch SW2 Configuration Option Settings
Mode Mode Pins [3:0] Mode SW2 [4:1] 2
JTAG 0000 ON,ON,ON,ON
QSPI32 0010 1 ON,ON,OFF,ON
SD 1110 OFF,OFF,OFF,ON
  1. Default switch setting.
  2. Switch OFF = 1 = High; ON = 0 = Low. See callout 11 in Table 1.

JTAG

AMD Vivado™ Design Suite or third-party tools can establish a JTAG connection to the Zynq UltraScale+ RFSoC through the FTDI FT4232 USB-to-JTAG/USB UART device (U29) connected to micro-USB connector (J24).

QSPI

Use the following steps to boot from the dual QSPI non-volatile configuration memory.

  1. Store a valid Zynq UltraScale+ RFSoC boot image into the QSPI flash devices (U11, U12, MIO[0:12] QSPI interface).
  2. Set the boot mode pins SW2 [4:1] as indicated in the table above for QSPI32.
  3. Either power-cycle or press the power-on reset (POR) pushbutton. SW2 is callout 11 in Figure 1.

SD

Use the following steps to boot from an SD card.

  1. Store a valid Zynq UltraScale+ RFSoC boot image file onto an SD card (plugged into SD socket J23) connected to the MIO[39:51] SD interface.
  2. Set the boot mode pins SW3 [4:1] as indicated in the table above for SD.
  3. Either power-cycle or press the power-on reset (POR) pushbutton. SW2 is callout 11 in Figure 1.

See the Zynq UltraScale+ Device Technical Reference Manual (UG1085) for more information about Zynq UltraScale+ RFSoC configuration options.