PS M.2 SATA Connector - PS M.2 SATA Connector - UG1390

ZCU216 Evaluation Board User Guide (UG1390)
Document ID
UG1390
Release Date
2023-12-07
Revision
1.2 English

[Figure 1, callout 31 and 32]

The M.2 SATA interface is provided for SATA SSD access using the PS-Side bank 505 GTR transceiver. The following figure shows M.2 connector U36.

The Socket 2 SATA adapter pinout with Key M is shown in the table below. SATA-A data connection is used for TX and SATA-B for RX. The M.2 connector U36 is a type 2242 (active component section 22 mm wide with overall length 42 mm form factor) used on Socket 2.

Figure 1. M.2 Connector
Table 1. M.2 Connector U40 Pinout
Pin Signal Signal Pin
74 3.3V GND 75
72 3.3V GND 73
70 3.3V GND 71
68 SUSCLK(32 kHz) (I)(0/3.3V) PEDET (GND-SATA) 69
ADD_IN CARD KEY M NC 67
ADD_IN CARD KEY M ADD_IN CARD KEY M
ADD_IN CARD KEY M ADD_IN CARD KEY M
ADD_IN CARD KEY M ADD_IN CARD KEY M
58 Reserved for MFG_CLOCK ADD_IN CARD KEY M
56 Reserved for MFG_DATA GND 57
54 NC NC 55
52 NC NC 53
50 NC GND 51
48 NC SATA-A+ 49
46 NC SATA-A- 47
44 ALERT# (O) (0/1.8V) GND 45
42 SMB_DATA (I/O) (0/1.8V) SATA-B- 43
40 SMB_CLK (I/O) (0/1.8V) SATA-B+ 41
38 DEVSLP (I) GND 39
36 NC NC 37
34 NC NC 35
32 NC GND 33
30 NC NC 31
28 NC NC 29
26 NC GND 27
24 NC NC 25
22 NC NC 23
20 NC GND 21
18 3.3V NC 19
16 3.3V NC 17
14 3.3V GND 15
12 3.3V NC 13
10 DAS/DSS (I/O) NC 11
8 NC GND 9
6 NC NC 7
4 3.3V NC 5
2 3.3V GND 3
- - GND 1

The M.2 adapter tie-offs as implemented on the ZCU216 board are listed in the following table.

Table 2. ZCU216 M.2 U40 Connector Tie-offs
M.2 Signal Name ZCU104 Tie-Off U40 Pin
SUSCLK No Connect 68
ALERT# No Connect 44
SMB_DATA No Connect 42
SMB_CLK No Connect 40
DEVSLP GND 38
DAS/DSS DNP Res to GND 10
PEDET No Connect 69
SATA-A GTR TX 49, 47
SATA-B GTR RX 43, 41

The M.2 U40 connector to RFSoC connections are listed in the following table.

Table 3. M.2 U40 Connections to the XCZU49DR Zynq UltraScale+ RFSoC
XCZU49DR (U1) Pin Net Name I/O Standard M.2 Connector U40
Pin Number Pin Name
AD36 GT3_SATA1_TX_P 1 49 SATA-A+
AD37 GT3_SATA1_TX_N 1 47 SATA-A-
AC38 GT3_SATA1_RX_P 1 41 SATA-B+
AC39 GT3_SATA1_RX_N 1 43 SATA-B-
  1. Series capacitor coupled, MGT I/F and I/O standards do not apply.

For more information, see PCI_Express_M.2_Specification_Rev1.1_TS_12092016_NCB on the PCI-SIG website.

The detailed RFSoC connections for the feature described in this section are documented in the ZCU216 board XDC file, referenced in Xilinx Design Constraints.