XPHY Interfaces with BLI Resources in Multiple Clock Regions - 2024.2 English - UG1388

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2024-12-18
Version
2024.2 English

In some devices, some of the I/O banks might have BLI resources in multiple PL clock regions. For example, in the following figure, the BLI registers are part of the interface paths of bank 709 in the xcvp1902 device.

Figure 1. BLI Resources Related to a Single I/O Bank Split Across Two Clock Regions

Banks with BLI resources split across multiple clock regions might not be able to achieve the same maximum performance as banks with BLI resources that are contained in a single clock region. For example, following are the best timing results achievable for the example shown in the previous figure.

Figure 2. Best Timing Results for BLI Resources Related to a Single I/O Bank Split Across Two Clock Regions

One approach to improving performance on these banks is to split the BLI loads on the outputs of the XPLL so that each CLKOUT pin of the XPLL drives only BLI registers in a single clock region. To do this, use two of the CLKOUT[0:4] pins to drive two separate groups of BLIs with each group confined to a single clock region. The XPLL has two deskew and phase control circuits. You can use the remaining two CLKOUT[0:4] outputs of the XPLL as feedback paths, each independently controlling the phases of the two BLI groups. The following figure shows an example of how to divide the loads shown in the previous figure into two separate groups.

Figure 3. BLIs Split into Single Clock Region Groups

By splitting the loads of the XPLL so that each CLKOUT pin clocks only BLIs in a single clock region, the timing for the split BLI groups is improved to the following.

Figure 4. Timing Results for BLIs Split into Single Clock Region Groups

For information on how to configure the XPLL for dual-feedback functionality, see the Versal Adaptive SoC Clocking Resources Architecture Manual (AM003).