XPHY Interface Timing - 2024.2 English - UG1388

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2024-12-18
Version
2024.2 English

XPHY logic is used for high speed interfaces in many Versal device designs. Achieving the maximum frequency possible on these interfaces requires proper placement of the registers of the interface along with clock phase adjustments on the XPLLs that typically create the clocks for the registers.