Vitis HLS simulation exclusively tests HLS code and is an integral part of the HLS development process. The scope of this simulation is a single top-level function, typically referred to as the DUT or kernel. The system supports two abstractions. These include untimed and RTL (cycle-accurate). The two abstractions are C simulation (Csim) and Co-simulation (Cosim).
In the Csim flow, you must validate the function to be synthesized with a test
bench using C simulation. A C test bench includes a main() top-level function, that calls the top-level function to be
synthesized.
In the Cosim flow, the HLS compiler generates RTL output code. This code automatically compares with the Csim result. The purpose of the Cosim flow is to verify the functional correctness after C synthesis.
Vitis HLS simulation is available through the Vitis unified software platform. For more information, refer to this link in the Vitis High-Level Synthesis User Guide (UG1399).