Vitis HLS simulation exclusively tests HLS code and is an integral part of the HLS development process. The scope of this simulation is a single top-level function, typically referred to as the DUT or kernel. Two abstractions are supported, untimed and RTL (cycle-accurate). These two abstractions are referred to as C simulation (Csim) and Co-simulation (Cosim), respectively.
In the Csim flow, the function to be synthesized must be validated with a test
bench using C simulation. A C test bench includes a main() top-level function, that calls the top-level function to be
synthesized.
In the Cosim flow, the RTL output code generated by the HLS compiler is automatically compared against the output of the Csim result. The purpose of the Cosim flow is to verify the functional correctness after C synthesis.
Vitis HLS simulation is available through the Vitis unified software platform. For more information, see this link in the Vitis High-Level Synthesis User Guide (UG1399).