Using Hard SLR Floorplan Constraints - 2025.1 English - UG1388

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)
Document ID
UG1388
Release Date
2025-06-25
Version
2025.1 English

For high target clock frequency designs, sufficient pipelining between the major hierarchies is required to ease global placement and SLR partitioning. When a design is challenging, SLR crossing points can change from run to run. In addition to defining SLR Pblocks, you can create additional Pblocks that are aligned to clock regions and located along the SLR boundary to constrain the crossing flip-flops. The following example shows a Versal xcvp1702 SSI device with SLL tiles that drive/are driven by SLR crossing nodes highlighted in cyan and with the following Pblocks:

  • 3 SLR Pblocks: SLR0, SLR1 and SLR2
  • 4 SLR-crossing Pblocks: SLR0_top_row, SLR1_bottom_row, SLR1_top_row, and SLR2_bottom_row
Figure 1. SLR-Crossing Pblock Example
Important: AMD recommends using CLOCKREGION ranges for SLR-crossing Pblocks. For Pblocks at the top of SLR0, the top two clock regions are required to capture all the SLLs that cross the SLR. These are clock regions with Y3 and Y4 coordinates. For Pblocks that do not span the entire width of the device, CLOCKREGION ranges with X coordinates closest to the CLOCK_ROOT X- coordinate have faster performance.
Tip: You can define SLR Pblocks by specifying a complete SLR. For example, resize_pblock pblock_SLR0 -add SLR0.
To determine the number of SLLs that can route directly from or to a cell within a Pblock, you can use the following command:
llength [[get_nodes SLL*/UBUMP* -filter {IS_CROSSING_SLRS} -of [get_tiles SLL* -of [get_nodes -of [get_tiles CLE* -of [get_sites -of [get_pblocks pb_slr_slr0_top]]]]]]]

For more information, see this link in Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).

Video: For information on using floorplanning techniques to address design performance issues, see the Vivado Design Suite QuickTake Video: Design Analysis and Floorplanning.