The Vivado Design Suite provides debug-related DRCs, which are selected as part of the default rule deck when report_drc is run. The DRCs check for the following:
- Block RAM resources for the device are exceeded because of the current requirements of the debug core.
- Non-clock net is connected to the clock port on the debug core.
- Port on the debug core is unconnected.
- CIPS/PS Wizard does not have
pl_resetn0enabled for the debug hub insertion flow.