Revision History - 2025.1 English - UG1388

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2025-06-25
Version
2025.1 English

The following table shows the revision history for this document.

Section Revision Summary
06/25/2025 Version 2025.1
General updates Added references to Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2.
Reducing Clock Insertion Delay in Versal Devices Added information on calibrated deskew.
Calibrated Deskew Added new section.
Using Hard SLR Floorplan Constraints Added recommendations for CLOCKREGION ranges.
Using SLR Crossing Registers Added recommendations for unused registers.
Improving NoC Performance by Optimizing NoC QoS Over Fabric Timing QoR Added new section.