The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 12/17/2025 Version 2025.2 | |
| Baselining the Design | Updated graphic. |
| Pre-Placement, Post-Placement, and Post-Physical Optimization | Added new section. |
| Prioritize Critical Logic Using the group_path Command | Added information on determining the priority level of a clock. |
| 06/25/2025 Version 2025.1 | |
| General updates | Added references to Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2. |
| Reducing Clock Insertion Delay in Versal Devices | Added information on calibrated deskew. |
| Calibrated Deskew | Added new section. |
| Using Hard SLR Floorplan Constraints | Added recommendations for CLOCKREGION ranges. |
| Using SLR Crossing Registers | Added recommendations for unused registers. |
| Improving NoC Performance by Optimizing NoC QoS Over Fabric Timing QoR | Added new section. |