After placement, delays are close to ideal routing, except for long and medium to high fanout nets that use more pessimistic delays. In addition, congestion and hold fixing impact are not accounted for in the net delays at this point, which make timing results optimistic.
AMD recommends running physical synthesis on all designs that do not meet timing after placement. This opportunistically fixes timing problems related to the following:
- Nets with high fanout
- Nets with drivers and loads that are far apart
- DSP and RAM blocks with sub-optimal pipeline usage
You can fix small WNS violations by adding positive clock skew. Clock skew is
accurately estimated at the post-place phase but the estimate might not be the final
skew. Both phys_opt_design and route_design can opportunistically alter clock skew to aid timing closure.
However, less clock skew is added during the phys_opt_design stage.
If you observe high skew, the router automatically resolves paths with high skew that have good setup margin. In addition, following are common solutions:
- Clock template selection
- In SSI technology devices, calibrated deskew
- BLI usage when interfacing to I/Os and AI Engines