NoC Simulation - NoC Simulation - 2026.1 English - UG1388

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)
Document ID
UG1388
Release Date
2026-07-22
Version
2026.1 English

NoC simulation support includes behavioral models. Models are available in SystemVerilog or SystemC. The SystemC model simulates much faster but is cycle approximate and less accurate compared to the SystemVerilog model.

Note: You can select your preferred simulation model using the IP Project Settings. Use the rtl setting for SystemVerilog and the tlm setting for SystemC. These settings apply to the entire project.

You can use both the SystemC and SystemVerilog models to verify functionality. Use SystemVerilog for performance analysis. You can simulate the NoC using simulators in the Vivado tools or using the hardware emulation flow provided by the Vitis tools.

For more information on the NoC simulation settings and performance tuning, refer to the following documents:

  • Refer to this link and this link in the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)
  • Refer to this link and this link in the Programmable Network on Chip (NoC2) LogiCORE IP Product Guide (PG406)
  • Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)

For more information on the AXI Traffic Generator, refer to the Versal Network on Chip Performance AXI Traffic Generator Tutorials available from the GitHub repository.