Some IP, such as the soft DDR memory controller, have a slightly different TX interface configuration than shown in previous examples. The following figure shows how two of the CLKOUT pins of a master XPLL can be used to clock the BLI register as well as a secondary XPLL which clocks the XPHY.
In this case, CLKOUT0 is used to clock the secondary XPLL, which then clocks the XPHY. The CLKOUT0 output can be affected by the feedback and phase shift of the master XPLL. This is different from the circuit in previous examples where the CLKOUTPHY output, which is not affected by the feedback and phase shift, is used to clock the XPHY. In such cases, it is important that the XPLL configuration disables the feedback and phase shift interface to CLKOUT0 so that the clock signal to the startpoint register can be adjusted independently from the clock signal to the XPHY. For information on how to configure the XPLL, see the Versal Adaptive SoC Clocking Resources Architecture Manual (AM003).