Improving Performance Through the CPM and PL PCIE - 2024.1 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2024-06-19
Version
2024.1 English

The Versal architecture supports multiple subsystems for PCIe, including integrated controllers for PCIe, integrated DMA/bridge functions, and soft IP for DMA/bridge functions. Performance improvements in the application of these subsystems is subsystem-specific. For information on these subsystems, see one of the following IP product guides:

  • Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)
  • Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
  • Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)
  • Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)
Note: For more information on debug, see the PCIe Debug K-Map available from the GitHub repository.