Hardware emulation simulates a complete Versal adaptive SoC system composed of the AI Engine, PS, and PL. Using the Vitis software platform, you can integrate blocks and functions targeting all three compute domains. The Vitis linker automatically generates a complete co-simulation setup involving RTL, SystemC, and QEMU models:
- RTL code simulates user PL kernels.
- The SystemC AI Engine simulator emulates code running on the AI Engines.
- QEMU emulates the embedded software code running on the PS.
- The simulator simulates IP blocks in the hardware platform as RTL or SystemC TLM, depending on the available or selected model types.
As a result, the abstraction of the Vitis hardware emulation is almost fully cycle-accurate. TLM models abstract some details of the Versal adaptive SoC platform to improve simulation speed.
The scope of the Vitis hardware emulation also defines its purpose. Hardware emulation allows you to simulate the entire design and test the interactions between the PL, PS, and AI Engine prior to implementation. Hardware emulation provides full debug visibility into all aspects of the application. This simplifies debugging complex problems compared to real hardware.
Hardware emulation is available through the Vitis unified software platform. For more information, refer to the AI Engine Tools and Flows User Guide (UG1076) and AI Engine Kernel and Graph Programming Guide (UG1079).
You can use AXI traffic generators as an alternative to using file-based inputs and outputs. In contrast to file-based inputs and outputs that are static and limited, AXI traffic generators are a dynamic way to produce and consume data. For more information, refer to the AXIS External Traffic Generator Feature Tutorial.
Using AXI traffic generators offers the following advantages:
- Allows you to reuse the same simulation set used during AI Engine simulation
- Allows you to abstract some of the blocks in your system with traffic generators, which are faster to simulate