The following figures show examples of a typical RX and TX XPHY-BLI interface. The XPHY and BLI registers are on separate clock networks. In both cases, the registers are clocked by a CLKOUT output of an XPLL. The XPHY is clocked by an output of another XPHY or by the CLKOUTPHY output of an XPLL. You can adjust the XPLL CLKOUT[0:4] outputs using the feedback and phase shift capabilities of the XPLL to help with timing closure on the XPHY-BLI paths.
The following figure shows a detailed view of the relevant connections of the XPLL from the TX example shown in the previous figure.
The blue feedback connection results in clock network delay removal to the BLI registers. The green connection provides a reference signal for the CLKOUT0 clock signal. By using the XPLL capabilities to adjust the phase output of CLKOUT3, you can advance or delay the clock signals to the BLI registers by up to a full clock cycle to improve the timing on the BLI to XPHY timing path.
The connections of the XPLL on the RX interface are similar. For more information on how to adjust the phase of the output clocks of the XPLL, see the Versal Adaptive SoC Clocking Resources Architecture Manual (AM003).
For the RX interface, because the BLI register is the destination of the timing path, a positive phase shift from the XPLL to the BLI clock pin improves setup timing while a negative phase shift improves hold timing. This is reversed for the TX interface because the BLI register is the startpoint of the timing path. That is, positive phase shift improves hold timing while a negative phase shift improves setup timing.
During implementation, the AMD Vivado™ tools have limited ability to improve timing on these interface paths because of the dedicated routing between the XPHY and BLI. The router can delay the clock signal to the BLI registers to address timing issues on the interface paths. Therefore, the ideal phase setting on the XPLLs of the RX interface is one that removes all hold violations on the paths and minimizes any remaining setup violations. The router can then delay the clock signal to the BLI destinations to resolve any setup violations remaining. For the TX interface, this is reversed. That is, the ideal phase setting removes all setup violations on the paths and minimizes any remaining hold violations that can then be resolved by the router by delaying the clock signals to the BLI startpoints of the TX interface paths.