Calibrated deskew is a hardware feature that performs calibration of programmable delays in the global clock network at device startup. By default, calibrated deskew is turned off for all clocks. When the calibrated deskew is enabled for a clock, decreased skew is achieved vertically, horizontally, and between SLRs. However, this approach also results in increased insertion delay on the clock due to the programmable delays. To enable calibrated deskew for a clock, set the GCLK_DESKEW property to CALIBRATED on the clock net driven by the BUFG. For example:
set_property GCLK_DESKEW CALIBRATED [get_nets -of [get_pins BUFGCE_inst/O]]Due to the increased insertion delay, calibrated deskew can degrade timing on:
- Synchronous CDC timing paths that are not using the MBUFG and are
using parallel BUFG
This is due to the increased min-max spread from the increased insertion delay.
- I/O timing paths between fabric and XPIO loads
This is due to the clock route to XPIO loads being faster and the common node always being at the clock root. In cases where the XPIO load is an IOB flip-flop, you can substitute a BLI flip-flop that allows for calibrated deskew because BLI resources exist in fabric.
Calibrated deskew is recommended to achieve the following:
- Reduce clock skew in the vertical and horizontal directions
- Maximize SLR crossing performance
To determine which clocks have calibrated deskew enabled, examine the GCLK Deskew column in the Clock Utilization report.
You must apply calibrated deskew to a clock before
place_design to affect the clock routing and the clock
skew throughout the placer flow. However, for a clock that was routed with calibrated
deskew disabled, you can evaluate the timing impact of skew reduction due to calibrated
deskew by using the update_clock_routing command on a
post-place design prior to running route_design. The
following script shows how to enable calibrated deskew on a post-place design and update
the clock tree routing using the update_clock_routing
Tcl command. Alternatively, you can turn off calibrated deskew on a previously enabled
clock net by setting the GCLK_DESKEW property value to OFF. AMD recommends running phys_opt_design
after updating the clock routing to fix any violations that might be introduced by
changing the GCLK_DESKEW setting.
route_design -unroute -nets [get_nets -of [get_pins bufg_inst/O]]
#Cannot specify USER_CLOCK_VTREE_TYPE when enabling Calibrated Deskew
set_property USER_CLOCK_VTREE_TYPE {} [get_nets -of [get_pins bufg_inst/O]]
set_property GCLK_DESKEW CALIBRATED [get_nets -of [get_pins bufg_inst/O]]
update_clock_routing -net [get_nets -of [get_pins bufg_inst/O]]
Calibrated deskew in Versal SSI technology devices is not supported for all clock root and clock expansion window combinations on all clock tracks. In general, the larger the clock expansion window, the lower the number of clock roots and tracks that are supported. The Vivado placer automatically selects the optimal clock root and track combination for a given clock expansion window. Off-center clock roots in clocking column X0, X1, and X9 do not support calibrated deskew. You can also apply the USER_CLOCK_ROOT constraint to select a clock root that supports the maximum number of clock tracks for calibrated deskew.
The following figures show the maximum number of clocks that can have calibrated deskew enabled for a given clock root and clock expansion window. For example, for a clock expansion window that covers SLR1 and SLR2, a clock root in X3Y7 can support 18 clock tracks with calibrated deskew enabled, whereas a clock root in X7Y7 can only support 4 clock tracks.
report_qor_suggestions Tcl command before placement to generate commands
that automatically set the GCLK_DESKEW property.