XPIO Global Clock Buffer Clock Enable Timing - XPIO Global Clock Buffer Clock Enable Timing - 2026.1 English - UG1387

Even at lower clock frequencies, it can be difficult to meet the setup timing requirement on a global clock buffer enable pin. The setup timing path challenges is due to the combination of:

• The late enable edge occurs when the launch clock uses global clock routing. It is followed by the route from the flip-flop. This route crosses the boundary logic interface (BLI) to reach the enable pin.
• The early capture clock edge arriving directly at the gated global clock buffer input pin without routing through the global clock network.

Figure 1. Global Clock Buffer Clock Enable Circuit

You can use the following techniques to improve timing to the global clock buffer enable pins:

• Use the HARDSYNC feature on the global clock buffers that use a three-stage internal synchronizer. This removes the timing requirement but incurs a three or four clock-cycle latency on the clock output. If more than one BUFGCE is controlled by the same CE register, they cannot start on the same clock edge. This loss of clock relationship between the input and the output clocks of the BUFGCE occurs. This makes it unsafe to time between the downstream clocks of the BUFGCE and other clocks of the design.
• Use a negative phase-shifted clock to drive the enable control logic and pull in the launch clock edge.
• Use the CLOCK_LOW_FANOUT constraint on the clock used to drive the enable control logic. This reduces the clock insertion delay on the source clock path by keeping it local to the adjacent clock region. The clock net must have a limited number of loads for this constraint to properly work.
• Use the BLI constraint on the flip-flop that directly drives the global clock buffer. The BUFGCE clock enable pins do not have an associated BLI flip-flop resource. Therefore, you must use a BUFGCE_DIV with a divide of 1 or a BUFGCTRL when using the BLI flip-flop.
• Use a cascaded buffer to drive the gated clock buffer and ensure the following outcomes:
  • Optimization does not remove the cascaded buffer.
  • Place the cascaded buffer in the same CLOCK REGION as the gated clock buffer.
  • The design balances the cascaded buffer and the buffer driving the enable control logic.
• In some cases, HARDSYNC supports CE timing closure. An MBUFGCE can be used with HARDSYNC. The MMCM input clock must phase-align the output clocks. You can use the MMCM digital deskew function.

The following figure shows an example circuit using the MMCM deskew to align the MBUFGCE clock outputs with the MMCM input clock.

• Align the MBUFGCE output clock edges with the CLKIN1 input of the MMCM to ensure synchronization:
  • The input clock (red net) connects to both the CLKIN1 and CLKIN1_DESKEW pins of the MMCM. One of the outputs of the MBUFGCE (blue net) is used as the reference signal for phase alignment and connects to the MMCM CLKFB1_DESKEW input. The frequency of the clock input to CLKFB1_DESKEW must match the frequency of the clock input to CLKIN1_DESKEW. In this example, the MBUFGCE O3 output has the same frequency as the input clock, so the design uses it as the feedback clock.
  • The MMCM CLKOUT1 output drives the input clock to the MBUFGCE. Enable the MMCM deskew circuit for the MMCM CLKOUT1 output to phase align the MBUFGCE clocks to the input clock. Set the MMCM property CLKOUT1_PHASE_CTRL to 2'b01 to accomplish this. For more information about MMCM properties, refer to this link in the Versal Adaptive SoC Clocking Resources Architecture Manual (AM003).
  • The LOCKED signal from the MMCM must not relate to the signal assertions of the CE and CLRB_LEAF pins of the MBUFGCE. The LOCKED signal does not assert until the deskew circuit has locked. The deskew circuits cannot achieve lock without an active clock feedback from the MBUFGCE.

    In the circuit above, the assertion circuit for CE and CLRB_LEAF uses the LOCKED_FB signal. The purple net represents the LOCKED_FB signal. The LOCKED_FB signal generates the CE and CLRB_LEAF signals for the MBUGGCE.

    • LOCKED_FB is an output from the MMCM used to indicate when the MMCM has achieved phase and frequency alignment of the reference clock and the feedback clock at the input pins. Phase alignment is within a predefined window and frequency matching within a predefined part per million (PPM) range. The MMCM automatically locks after power on; no extra reset is required. The LOCKED1/2_DESKEW outputs indicate if the optional deskew circuit is used and has locked. The LOCKED output signals that the LOCKED_FB and LOCKED1/2_DESKEW circuits have achieved lock.
  • The CLRB_LEAF input on the MBUFG primitive asynchronously resets the BUFDIV_LEAF dividers. Perform this reset if the MMCM loses lock. For proper MBUGCE operation, assert CLRB_LEAF while CE is inactive. The Multi-Clock Buffer (MBUFG) section details the timing relationship of CE and CLRB_LEAF. Instance MBUFGCE_CE_1_DLY_inst above uses the LOCKED_FB signal from the MMCM to create the proper assertion sequence for the CE and CLRB_LEAF pins of the MBUFGCE.