XPIO Global Clock Buffer Clock Enable Timing - 2025.2 English - UG1387

Even at lower clock frequencies, it might be difficult to meet the setup timing requirement on a global clock buffer enable pin. The setup timing path challenges is due to the combination of:

• The late enable edge where the launch clock uses global clock routing followed by the route from flip-flop crossing the boundary logic interface (BLI) to reach the enable pin.
• The early capture clock edge arriving directly at the gated global clock buffer input pin without routing through the global clock network.

Figure 1. Global Clock Buffer Clock Enable Circuit

You can use the following techniques to improve timing to the global clock buffer enable pins:

• Use the HARDSYNC feature on the global clock buffers that use a three-stage internal synchronizer. This removes the timing requirement but incurs a three or four clock-cycle latency on the clock output. If there are more than one BUFGCEs controlled by the same CE register, there is no guarantee that they start up on the same clock edge. This loss of clock relationship between the input and the output clocks of the BUFGCE makes it unsafe to time between the clock(s) in the downstream of the BUFGCE with other clocks of the design.
• Use a negative phase-shifted clock to drive the enable control logic and pull in the launch clock edge.
• Use the CLOCK_LOW_FANOUT constraint on the clock used to drive the enable control logic. This reduces the clock insertion delay on the source clock path by keeping it local to the adjacent clock region. The clock net must have a limited number of loads for this constraint to properly work.
• Use the BLI constraint on the flip-flop that directly drives the global clock buffer. The BUFGCE clock enable pins do not have an associated BLI flip-flop resource. Therefore, you must use a BUFGCE_DIV with a divide of 1 or a BUFGCTRL when using the BLI flip-flop.
• Use a cascaded buffer to drive the gated clock buffer and ensure the following:
  • Cascaded buffer is not optimized away
  • Cascaded buffer is placed in the same CLOCK REGION as the gated clock buffer
  • Cascaded buffer and buffer driving the enable control logic are balanced
• In some cases when using HARDSYNC for CE timing closure, an MBUFGCE can be used with an additional requirement that the output clocks be phase-aligned with the MMCM input clock. You can use the MMCM digital deskew function.

The following figure shows an example circuit using the MMCM deskew to align the MBUFGCE clock outputs with the MMCM input clock.

• To ensure that the MBUFGCE output clock edges are aligned with the CLKIN1 input of the MMCM:
  • The input clock (red net) connects to both the CLKIN1 and CLKIN1_DESKEW pins of the MMCM, while one of the outputs of the MBUFGCE (blue net) is used as the reference signal for phase alignment and connects to the MMCM CLKFB1_DESKEW input. The frequency of the clock input to CLKFB1_DESKEW must match the frequency of the clock input to CLKIN1_DESKEW. In this example, the MBUFGCE O3 output has the same frequency as the input clock, so it is used as the feedback clock.
  • The MMCM CLKOUT1 output drives the input clock to the MBUFGCE. To phase align the MBUFGCE clocks to the input clock, the MMCM deskew circuit must be enabled for the MMCM CLKOUT1 output. This is accomplished by setting the MMCM property CLKOUT1_PHASE_CTRL to 2'b01. For more information about MMCM properties, see this link in the Versal Adaptive SoC Clocking Resources Architecture Manual (AM003).
  • The signal assertions of the CE and the CLRB_LEAF pins of the MBUFGCE must not be related to the LOCKED signal from the MMCM. The LOCKED signal does not assert until the deskew circuit has locked, but the deskew circuits cannot achieve lock without an active clock feedback from the MBUFGCE. In the circuit above, the assertion circuit for CE and CLRB_LEAF (MBUFGCE_CE_1_DLY_inst) instead uses the LOCKED_FB signal (purple net) to generate the CE and CLRB_LEAF signals for the MBUGGCE.
    • LOCKED_FB is an output from the MMCM used to indicate when the MMCM has achieved phase and frequency alignment of the reference clock and the feedback clock at the input pins. Phase alignment is within a predefined window and frequency matching within a predefined part per million (PPM) range. The MMCM automatically locks after power on; no extra reset is required. The LOCKED1/2_DESKEW outputs indicate if the optional deskew circuit is used and has locked. The LOCKED output signals that the LOCKED_FB and LOCKED1/2_DESKEW circuits have achieved lock.
  • The CLRB_LEAF input on the MBUFG primitive is used to asynchronously reset the BUFDIV_LEAF dividers, which is required if the MMCM loses lock. For proper MBUGCE operation, the CLRB_LEAF must be asserted while CE is inactive. The timing relationship of CE and CLRB_LEAF is detailed in the Multi-Clock Buffer (MBUFG) section. Instance MBUFGCE_CE_1_DLY_inst above uses the LOCKED_FB signal from the MMCM to create the proper assertion sequence for the CE and CLRB_LEAF pins of the MBUFGCE.