Vitis HLS supports the following flow:
- Vivado IP Flow
- Supports a variety of interfaces and data transfer protocols, provides multiple design choices, and is more flexible. However, you must handle the integration and management of the IP. For information on how to enable this flow in Vitis HLS, refer to this link in the Vitis High-Level Synthesis User Guide (UG1399).
- Vitis Kernel Flow
- Supports a specific set of interfaces and is more restrictive. This more structured flow allows correct-by-construction integration of HLS blocks with Vitis extensible platforms. It enables seamless integration with the flexible runtime (XRT) software stack. This greatly simplifies the hardware/software integration process. For information on how to enable this flow in Vitis HLS, refer to this link in the Vitis High-Level Synthesis User Guide (UG1399).
When targeting AMD Versal™ devices, you must configure the Vitis HLS project based on the design flow (traditional design flow or platform-based design flow). Configure the project according to the usage of the resulting block in the overall project. The following table shows this configuration.
| Design Flow | Vitis HLS Output | Flow | Targeted User |
|---|---|---|---|
| Traditional design flow | Integrated with other RTL and IP blocks | Vivado IP flow | Hardware designer |
| Platform-based design flow | Integrated in the extensible platform | Vivado IP flow | Hardware designer |
| Platform-based design flow | Linked as a kernel to the extensible platform | Vitis kernel flow | Hardware designer or software developer |
Recommended:
AMD strongly recommends using Vitis HLS in the Vitis kernel flow
when you use Vitis HLS in the platform-based design
flow. This approach generates a block that the Vitis v++ linker automatically link to the extensible platform in a correct-by-construction
manner.