Enter the I/O timing constraints, then review the analysis of timing on the I/O
paths. Check the amount of slack violation for both setup and hold checks. By using the
timing reports from/to all ports for both setup and hold analysis (that is, delay type = min_max), you can verify that:
- The correct clocks and clock edges provide the reference for the delay constraints.
- The expected clocks are launching and capturing the I/O data inside the device.
- You can reasonably fix the violations by placing them correctly or by setting the proper delay line tap configuration. If this is not the case, review the I/O delay values entered in the constraints. Evaluate whether the I/O delay values are realistic. Determine if you must modify the design to meet timing.