Define and apply all design clocks in memory. Then, use the report_clocks command to verify the waveform of each clock and the
relationship between master and generated clocks.
Clock Period Waveform Attributes Sources
sysClk 10.00000 {0.00000 5.00000} P {sysClk}
clkfbout 10.00000 {0.00000 5.00000} P,G {clkgen/mmcm_adv_inst/CLKFBOUT}
cpuClk 20.00000 {0.00000 10.00000} P,G {clkgen/mmcm_adv_inst/CLKOUT0}
…
====================================================
Generated Clocks
====================================================
Generated Clock : cpuClk
Master Source : clkgen/mmcm_adv_inst/CLKIN1
Master Clock : sysClk
Edges : {1 2 3}
Edge Shifts : {0.000 5.000 10.000}
Generated Sources : {clkgen/mmcm_adv_inst/CLKOUT0}Verify that at least one clock covers all internal timing paths. The Check Timing report provides two checks for that purpose:
- no_clock
- A defined clock does not reach any active clock pin.
- unconstrained_internal_endpoint
- The system reports all the data input pins of sequential cells that have a timing check relative to a clock. However, you have not defined the clock.
If both checks return zero, the timing analysis coverage is high.
Run the XDC and Timing Methodology checks to verify that you have defined all clocks on recommended netlist objects. This approach avoids any constraint conflict or inaccurate timing analysis scenario.
Use the following command to run these checks:
report_methodology -checks [get_methodology_checks {TIMING-* XDC*}]