The Versal Adaptive SoC design methodology emphasizes the importance of monitoring design budgets, such as area, power, latency, and timing. It also emphasizes correcting the design from early stages as follows:
- Leverage as many Versal adaptive SoC integrated blocks as possible, using the network
on chip (NoC) for the higher bandwidth connections and validating the design
performance at the block diagram level.
Efficient data movement around the device between blocks is critical. You must explore various block connectivity options via the NoC or the programmable logic (PL). Maximizing the use of the NoC frees up PL resources and reduces floorplanning or implementation challenges later on.
- Create optimal RTL constructs with AMD
templates, and validate your RTL with methodology DRCs before synthesis, after
elaboration.
The Vivado tools use timing-driven algorithms throughout, so you must properly constrain the design from the beginning of the design flow.
- Perform timing analysis after synthesis.
To specify correct timing, you must analyze the relationship between each master clock and related generated clocks in the design. The Vivado tools time each clock interaction unless you explicitly declare it as an asynchronous or false path.
- Validate timing closure feasibility for each major
PL IP or block diagram by running out-of-context synthesis and implementation.
Identifying the right design or flow option changes is complex. This complexity increases when addressing timing, performance, or power issues when analyzing the complete design. By validating each sub-portion of the design, you reduce the convergence risk later in the design cycle. AMD recommends overconstraining the design clocks by up to 10% during out-of-context implementation. You can add a Pblock to model a high utilization scenario.
- Meet timing using the right constraints before proceeding to the next design stage.
You can accelerate overall timing and implementation convergence by following this recommendation and by using the interactive analysis environment of the Vivado Design Suite.
Tip: You can achieve further acceleration by combining these recommendations with the HDL design guidelines in this guide.
The following figure shows this recommended design methodology.
The synthesis completes when it meets the design goals with a positive margin or a relatively small negative timing margin. For example, if post-synthesis timing is not met, placement and routing results are not likely to meet timing. However, you can still go ahead with the rest of the flow even if timing is not met. Implementation tools can close timing if they can allocate the best resources to the failing paths.
In addition, proceeding with the flow provides a more accurate understanding of the negative slack magnitude, which helps you determine how much you need to improve the post-synthesis worst negative slack (WNS). You can use this information when you return to the synthesis stage with improvements to HDL and constraints.