Using the IMUX Register Constraint - Using the IMUX Register Constraint - 2026.1 English - UG1387

Optional flip-flop stages exist in the IRI_QUAD sites that drive Hard Macros in the PL. The input routing MUXes drive these IMUX registers (IMR). The organization of the IMUX registers includes four IRI_QUAD sites per interface tile.

Refer to this link in the Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388) for more information. It explains how to use IMUX registers to improve timing to Hard Macros.

The IMRs can optimize the interface timing by registering signals driving into a hard block such as a block RAM, DSP, GT_QUAD, and so on.

The following figure on the left shows the IRI_QUAD sites highlighted in cyan that drive a set of RAMB18 and RAMB36 sites marked in red. On the right side, the view zooms in on one IRI_QUAD. The figure highlights the IMUX registers in cyan.

IMR flip-flop resources have the following restrictions:

• IMR only supports flip-flops with asynchronous clear (FDCE) or a synchronous reset (FDRE).
• IMR only supports FDCE and FDRE with INIT value of 0.
• All IMR flip-flops in a site must share the same active CLR signal or inactive GND R signal.
• FDCE and FDRE can be mixed in a site only if the CLR pin and R-pins are tied to GND.
• All IMR flip-flops in a IRI_QUAD site must share the same CE signal.
• Use only Data IMR Bels. Versal devices do not support Control IMR Bels.

By default, the tool avoids placing flip-flops in IMR flip-flop resources when they connect only to a hard block. The Vivado tools must use the IMR constraint to place flip-flops in the IMR flip-flop resources. If the IMR constraints are violated, the tools place the flip-flop in the CLB. Nets of CLB flip-flops interfacing with resources using the IMR perform a route-through of the IMR flip-flop resources.

The following example, use the IMR constraint for flip-flops in an IRI_QUAD. These flip-flops drive BLI registers, which in turn drive MBUFGCE_DIV/CE. Select BLI (highlighted in magenta) and IMR (highlighted in cyan) sites to obtain the optimal setup/hold window for registers driving the MBUFGCE_DIVE/CE pins.

set_property IMR TRUE [get_cells {control_SLR1_ce_reg control_SLR2_ce_reg}]