You can use the GCLK_DESKEW property to control calibrated deskew for a clock net. By default it is OFF. When you enable calibrated deskew, the system ignores the USER_CLOCK_VTREE_TYPE property on the calibrated net. For devices that support calibrated deskew, enabling calibrated deskew lowers intra-clock (and same MBUFG driver inter-clock) skew but results in longer insertion delays.
For some clocking topologies, it is more important to minimize insertion delay, while others, a lower skew is more beneficial. Typically, designs that benefit from lower insertion delay have:
- I/O timing paths
- Inter-clock timing paths
Designs that benefit from lower skew typically have:
- Higher performance clocks over 350 MHz
- Clocks with a high number of clock loads
For more information on default calibrated deskew settings for different Versal devices, refer to the Versal Adaptive SoC Clocking Resources Architecture Manual (AM003).
To enable calibrated deskew, you must set the GCLK_DESKEW property on the net segment directly driven by the clock buffer. Following is an example:
set_property GCLK_DESKEW CALIBRATED [get_nets -of [get_pins clkgen/BUFG_clkout2_inst/O]]Refer to this link in the Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388) for more information on calibrated deskew. The guide also provides details on other clock tree properties.