The CLOCK_LOW_FANOUT constraint contains the loads of a clock buffer within a single clock region. You can set the CLOCK_LOW_FANOUT constraint on a clock net segment directly driven by a global clock buffer or on a list of flip-flops.
Constraint Example for Clock Nets Driven by an XPIO Global Clock Buffer
Set the CLOCK_LOW_FANOUT property on a clock net segment directly driven by a global clock buffer in an XPIO bank. Ensure the fanout of the global clock buffer is less than 4000 loads. The clock region(s) contain the placement of the loads. BLI sites connect these regions to the XPIO bank of the global clock buffer. This can be one or two clock regions vertically adjacent to the XPIO bank.
The following example shows the CLOCK_LOW_FANOUT constraint applied to the
clock net segment driven by a global clock buffer placed in XPIO bank 704. The input
clock port, CLK_P/CLK_N has a PACKAGE_PIN
assignment to a GCIO located in the XPIO bank 704 (clock region X4Y0) and drives an
XPLL. The XPLL drives a global clock buffer that subsequently drives the clock
network consisting of 1359 loads, including both BLI and non-BLI registers.
The global clock buffer loads reside in the clock regions. These regions are directly above XPIO bank 704 (clock regions are X3Y1 and X4Y1). The following figure shows this placement.
# PACKAGE_PIN BM26/BN27 - High Performance XPIO
set_property PACKAGE_PIN BN27
set_property IOSTANDARD LVDS15 [get_ports CLK_N]
set_property PACKAGE_PIN BM26
set_property IOSTANDARD LVDS15 [get_ports CLK_P]
set_property CLOCK_LOW_FANOUT TRUE [get_nets -of [get_pins BUFG_clkout1_inst/O]]Constraint Example for Clock Nets Driven by an HDIO Global Clock Buffer
Set the CLOCK_LOW_FANOUT property on a clock net segment directly driven by a global clock buffer in an HDIO CLOCK_REGION. The fanout of the global clock buffer is less than 4000 loads. The placement of the loads remains within the same CLOCK_REGION as the global clock buffer.
The following example shows the CLOCK_LOW_FANOUT constraint applied to the
clock net segment directly driven by a global clock buffer placed in the HDIO. The
input clock port, clkIn has a PACKAGE_PIN
assignment to a GCIO located in the HDIO CLOCK_REGION X0Y4 and drives a DPLL. The
DPLL drives a global clock buffer that subsequently drives the clock network with
128 loads. The placement of all loads of the global clock buffer is in the
CLOCK_REGION X0Y4.
# PACKAGE_PIN L35 - High Density HDIO IOBank 306 - CLOCK_REGION X0Y4
set_property PACKAGE_PIN L35 [get_ports clkIn]
set_property IOSTANDARD LVCMOS33 [get_ports clkIn]
set_property CLOCK_LOW_FANOUT TRUE [get_nets -of [get_pins BUFG_clkout1_inst/O]]Constraint Example for Flip-Flops
Set the CLOCK_LOW_FANOUT constraint on a list of flip-flops that a global
clock buffer drives. This causes opt_design to
create a new parallel global clock buffer to isolate the flip-flops. During place_design, the newly created parallel global clock
buffer drives the isolated flip-flops. A single clock region contains these
flip-flops.
set_property CLOCK_LOW_FANOUT TRUE [get_cells safeClockStartup_reg[*]]The design includes an always-on clock network that initially drives more than
4000 loads. These loads include flip-flops which are part of the clock gating
synchronization circuit. This circuit is used to clock gate other logic. The
following schematics show the clock gating synchronization circuit and additional
logic connected to the always-on clock network before opt_design. After opt_design, the
schematic show a new parallel global clock buffer that isolates the clock gating
synchronization circuit.
The Device window of the fully implemented design shows the clock gating synchronization circuit with green markers. It also shows the always-on logic. Additionally, it displays the clock-gated logic. The placement of the clock gating synchronization circuit in a CLOCK_REGION minimizes the insertion delay from the BUFG in the XPIO.