Flip-flop stages exist in the boundary logic interface (BLI) between the programmable logic (PL) and the high-performance XPIO. Flip-flop stages also exist between the PL and AI Engine interface tiles. The BLI flip-flop resources can optimize the interface timing by registering signals coming into and going out of the PL. BLI flip-flop resources have the following restrictions:
- BLI only supports flip-flops with asynchronous clear (FDCE) or a synchronous reset (FDRE) with the R-pin tied to GND.
- BLI only supports FDCE and FDRE with INIT value of 0.
- All BLI flip-flops in a site must share the same active CLR signal or inactive GND R signal.
- You can mix FDCE and FDRE in a site only if you tie the CLR pin and R-pins to GND.
- All BLI flip-flops in a site must share the same CE signal.
By default, the tool does not place flip-flops in BLI flip-flop resources. This occurs if the flip-flops are simply connected to an XPIO bank or AI Engine interface tile resources. Use the BLI constraint to place flip-flops in the BLI flip-flop resources with the Vivado tools.
If the restrictions prevent meeting the BLI constraint, the tool places the flip-flop in the PL. Nets of PL flip-flops interfacing with resources using the BLI perform a route-through of the BLI flip-flop resources. The following example uses the BLI constraint for flip-flops in BLI resources that drive a flip-flop in the XPIO IOB. The example also demonstrates a PL flip-flop driving a flip-flop in the XPIO IOB. It shows the route from the BLI through the BLI flip-flop resources.
set_property BLI TRUE [get_cells myIntf/myBLI_reg]For more information on BLI in XPIO banks, refer to this link in the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).
For more information on the BLI constraint, refer to BLI in Vivado Design Suite Properties Reference Guide (UG912).