Use a primary clock, such as an incoming board clock, when it directly controls the I/O path sequential cells. Ensure it does not traverse any clock modifying block. I/O delay lines do not qualify as clock-modifying blocks because they only affect the clock insertion delay, not the waveform. The two examples in Defining Input Delays and Defining Output Delays show this case. Most of the time, the external device also has its interface characteristics defined with respect to the same board clock.
An HDIO DPLL inside the device compensates the primary clock using the zero hold violation (ZHOLD) mode. The I/O paths sequential cells connect to a phase detector deskewed internal copy, such as a generated clock, of the primary clock. Because the waveforms of both clocks are identical, AMD recommends using the primary clock as the reference clock for the input/output delay constraints.
The constraints are identical to the example provided in Defining Input Delays because the HDIO ZHOLD DPLL acts like a clock buffer with a negative insertion delay, which corresponds to the amount of compensation.