AMD recommends using I/O constraint templates for the source synchronous interfaces. You can write the source synchronous constraints in several ways. The Vivado Design Suite provides templates based on the default timing analysis path requirement.
The syntax is simpler. Adjust the delay values to account for setup analysis. Use launch and capture edges (1-cycle or 1/2-cycle) instead of same edge (0-cycle). The timing reports can be more difficult to read as the clock edges do not directly correspond to the active ones in hardware.
You can navigate to these templates in the Vivado IDE through .