Using Vitis HLS in the Vitis Kernel Flow - Using Vitis HLS in the Vitis Kernel Flow - 2026.1 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2026-07-22
Version
2026.1 English

When targeting Versal devices, the platform-based design flow allows programming most of the device using the C++ language:

  • You can write the software application running on the PS in C/C++.
  • You can write the AI Engine graph in C/C++.
  • You can write PL kernels in C/C++ and compile them to hardware using the Vitis HLS tool.