To constrain clocks, you can assign placement constraints as follows:
- On a clock input at the I/O port
Assigning a PACKAGE_PIN constraint for a clock on a GCIO or assigning a LOC to an IOB affects the clock network. Place the MMCM/XPLL/DPLL and clock buffers directly connected to the input port in the same clock region.
- On MMCM/XPLL/DPLLs
The clock buffers directly connected to the MMCM/XPLL/DPLL outputs are automatically placed in the same clock region. The input clock ports connected to the MMCM/XPLL/DPLL inputs are also automatically placed in the same clock region. An input clock port and an MMCM/XPLL/DPLL are directly connected. They are constrained to different clock regions. You must manually insert a clock buffer.
In that case, you must set a CLOCK_DEDICATED_ROUTE constraint on the net connected to the MMCM/XPLL/DPLL.
- On a GT*_QUAD or IBUFDS_GT* cell
The cell drives the BUFG_GTs that reside in the same clock region.
Only use LOC constraints to place high fanout clock buffers in Versal devices if the following conditions are true. You understand the entire clock tree of the design. Placement is consistent in the design. Even after taking these precautions, collisions can occur during implementation due to design or constraint changes.