Using Clock Modifying Blocks (MMCM, XPLL, and DPLL) - Using Clock Modifying Blocks (MMCM, XPLL, and DPLL) - 2026.1 English - UG1387

You can use an MMCM, XPLL, or DPLL to change the overall characteristics of an incoming clock. The MMCM conditions and controls clock characteristics, such as:

• Creating tighter control of phase
• Filtering jitter in the clock
• Changing the clock frequency
• Correcting or changing the clock duty cycle

To use an MMCM, XPLL, or DPLL, you must coordinate several attributes. This coordination ensures the MMCM operates within specifications. It also ensures the MMCM delivers the required clocking characteristics on its output. For this reason, AMD highly recommends that you use the Clocking Wizard to properly configure this resource.

You can also directly instantiate an MMCM, XPLL, or DPLL, which allows even greater control. However, be sure to use the proper settings to avoid causing the following issues:

• Increasing clock uncertainty due to increased jitter
• Building incorrect phase relationships
• Making timing closure more difficult
  Important: Use the Clocking Wizard to configure the MMCM or PLL. By default, the Clocking Wizard configures the MMCM for low output jitter using reasonable power characteristics.

You can change the settings in the Clocking Wizard based on your goals. This can further minimize jitter. It can also improve timing. However, this comes at the cost of higher power. Alternatively, you can reduce power but increase output jitter.

When using an MMCM, XPLL, or DPLL, you must do the following:

• Do not leave any inputs floating. Relying on synthesis or other optimization tools to tie off the floating values is not recommended, because the values can be different than expected.
• Connect RST to the user logic, so that it can be asserted by logic controlled by a reliable clocking source. Grounding RST causes problems when the clock interrupts.
• Use LOCKED output in the implementation of reset. For example, hold the synchronous logic clocked from the PLL in reset until LOCKED is asserted. The LOCKED signal must be synchronized before it is used in a synchronous portion of the design. AMD recommends adding LOCKED to a processor map so it is visible when debugging.
• Confirm the connectivity between CLKFBIN and CLKFBOUT. Include the BUFG in the feedback path if the MMCM output clock needs phase alignment with the input clock. This is necessary when using BUF_IN compensation mode.
• To avoid the MMCM, XPLL, or DPLL phase error timing penalty on synchronous clock domain crossing paths in Versal devices, use MBUFG* primitives that use leaf-level division. If using MBUFG* primitives is not possible, consider using parallel BUFGCE_DIVs from a single CLKOUT port instead of individual BUFGCEs from multiple CLKOUT ports.