After defining all the primary clocks, use the Clock Networks or Check Timing
(no_clock) reports to identify the clock tree
portions without a timing clock. Then, define the generated clocks accordingly.
It is sometimes difficult to understand the transformation performed by a cone of logic on the master clock. In this case, you must adopt the most conservative constraint. For example, the source pin is a sequential cell output. The master clock is at least divided by two, so the proper constraint must be, for example:
create_generated_clock -name clkDiv2 -divide_by 2 \
-source [get_pins fd/C] [get_pins fd/Q]Finally, if the design contains latches, the latch gate pins need to be reached by
a timing clock. The system reports Check Timing (no_clock) if the constraint is missing. You can follow the examples above
to define these clocks.