You can use the set_input_delay and set_output_delay constraints without specifying the related
clock. The Vivado Design Suite timing engine analyzes
the design and associates each port with all the sampling clocks automatically. Then by
reporting timing on the I/O paths, you can see how the tool constrained each I/O port.
This is convenient for quickly constraining a design. However, generic constraints can
become a problem if they are too generic and do not model the hardware reality
accurately.