USER_CLOCK_ROOT assignment in Versal devices differs slightly from UltraScale devices due to changes in the clocking architecture. In Versal devices, not all clock regions have a vertical clock spine. You cannot use these clock regions for USER_CLOCK_ROOT assignment.
The following figure shows the locations of the vertical clock spines. The clock spines highlighted in blue are adjacent to the vertical NoC column at the boundary of two clock regions. The Vivado tools allow setting USER_CLOCK_ROOT to the left clock region of these clock spines. The diagram highlights the vertical clock spines in the transceiver Quad columns on the left and right sides of the device in purple.
You can assign a USER_CLOCK_ROOT to any clock region in the transceiver Quad columns. Assigning a USER_CLOCK_ROOT to a clock region in the leftmost transceiver Quad column blocks the clock. This occurs above the PS. The clock cannot reach any loads in the clock regions on the same row as the PS.
In addition, clocks sourced from XPIO cannot have their USER_CLOCK_ROOT assigned to the leftmost transceiver Quad column above the PS. This restriction exists because the clock cannot route over the PS. The clock must route along the VNoC column. The clock regions highlighted in green indicate legal USER_CLOCK_ROOT assignments, and the clock regions in red indicate illegal clock root assignments.
The following figure shows the USER_CLOCK_ROOT set to clock regions X0Y2, X0Y3, or X0Y4. In these cases, the clock cannot reach loads in clock regions X*Y1.
In the following example, the USER_CLOCK_ROOT constraint is illegal. The constraint sets the clock region to the right of the vertical clock spine.
set_property USER_CLOCK_ROOT X4Y3 [get_nets -of [get_pins BUFGCE_DIV_inst/O]]In this case, the placer issues a message and assigns a legal CLOCK_ROOT to the net such as CLOCK_REGION X3Y3.
In addition to the general USER_CLOCK_ROOT rules listed above for Versal SSI technology devices, any clock spanning more than one SLR must have a clock root located on the clock region row below a SLR boundary. If the USER_CLOCK_ROOT constraint is set to any other clock region, the placer ignores the constraint to create a balanced clock tree and minimize clock skew.