If your design consists of PL components only (RTL and IP only), you can use the AMD Vivado™ tools to generate a programmable device image (PDI) to program the Versal device. Like previous architectures, design sources are added to the Vivado tools and compiled through the Vivado implementation flow.
Following are additional important considerations:
- The hardened DDR memory controllers and HBM controllers are only accessible through the NoC IP. To use the DDR memory controller or HBM controllers, your design must include NoC IP.
- Hardware debug cores connect through the CIPS/PS Wizard IP by default. JTAG is still available but no longer the preferred flow. You must be familiar with changes to the hardware debug connectivity and flow.
Use Vivado IP integrator to instantiate, configure, and connect the CIPS/PS Wizard IP, the NoC/DDR memory controller IP, and hardware debug IP to take advantage of block design automation when iterating through design changes. Vivado IP integrator supports GT IP and connectivity IP (such as MRMAC IP), simplifying GT-based design creation and I/O planning.
You can integrate the complete design with the Vivado IP integrator using custom packaged IP, RTL module referenced blocks, and other IP available through the IP catalog. Alternatively, use the Vivado IP integrator to configure and connect critical Versal adaptive SoC IP (such as the CIPS/PS Wizard IP and the NoC/DDR IP). Then, instantiate the resulting block design in the RTL design. For more information, see this link in the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994).