The Vivado Design Suite timing engine models the I/O paths like register-to-register paths. However, you must define a constraint to model the part of the path delay located outside the device. When analyzing internal paths, minimum and maximum delays are considered for both setup and hold analysis. This is also true for I/O paths. For this reason, it is important to describe both min and max delay conditions.
By default, the system analyzes the I/O timing paths as single-cycle paths. This means the following:
- In maximum delay analysis (setup), the system captures data one clock cycle after the launch edge for single data rate interface. For a double data rate interface, it captures data half clock cycle after the launch edge.
- The same clock edge launches and captures the data for minimum delay analysis (hold).
A source synchronous interface can time the relationship between clock and I/O data differently if necessary. In that case, you must specify different I/O delays. Additional timing exceptions must also be specified. This corresponds to an advanced I/O timing constraints scenario.