System Design Types - System Design Types - 2026.1 English - UG1387

AMD Versal™ adaptive SoCs are heterogeneous compute platforms with multiple compute engines. You can map many applications on a Versal adaptive SoC. These include signal processing for wireless systems, machine learning inference, and video processing algorithms.

Versal adaptive SoCs deliver high system bandwidth with high-speed serial I/Os, network on chip (NoC), and various memory controllers (DDR4/LPDDR4/DDR5). It also includes HBM controllers and additional hard IP.

The Versal portfolio contains several different product lines:

• Versal Prime Series Gen 2
• Versal Prime Series
• Versal Premium Series
• Versal HBM Series
• Versal RF Series
• Versal AI Core Series
• Versal AI Edge Series Gen 2
• Versal AI Edge Series

The following figure shows the different system design types and design flows supported for each Versal device series.

Figure 1. System Design Types

The following table shows the system design types and design flows supported for each Versal device series. The table shows that most design flows build a platform.

The following is a summary of each system design type:

Hardware-only system

Programmable logic (PL) has configurable logic blocks (CLBs), block RAM, UltraRAM, and DSP engine designs. Create this system using the traditional design flow.

Embedded system

Embedded processing system with software running on the application processors (APU) or real-time processors (RPU) and hardware content in the PL. Create this system using either the traditional or platform-based design flow.

Embedded AI Engine system

Embedded processing system with software running on the APU or RPU, hardware content in the PL, and algorithmic content in the AI Engine. Create this system using the platform-based design flow.

Following are the design flows for Versal adaptive SoCs:

Traditional design flow

The entire PL portion of the system is defined in a single AMD Vivado™ project. This project must include the foundational Versal hardware IP blocks. Examples are Control, Interface, and Processing System (CIPS), Processing System (PS Wizard) , NoC, I/O controllers, and custom RTL or IP blocks required for the project. Add design sources to the Vivado tools and compile them through the Vivado implementation flow. If the system consists only of PL components, the Vivado tools generate a programmable device image (PDI) to program the Versal device. If the system also includes embedded software content, the software application is developed in the AMD Vitis™ environment on top of the fixed hardware design exported from the Vivado tools. This flow is similar to the one traditionally used for AMD Zynq™ UltraScale+™ MPSoCs.

Platform-based design flow

The system divides the hardware and it includes a reusable base platform developed in Vivado. It also includes extensions to the base hardware developed in Vitis. These connect through a well-defined set of connectivity interfaces within an extensible region of the base platform.

Most hardware design development happen in Vivado. Vitis develops and integrates parts of the design. Specify these parts in C++ rather than using a hardware description language (HDL). Examples of the latter include AI Engine graphs and kernels, as well as kernel functions targeting PL compiled through high-level synthesis (HLS).

You choose how to partition your design between base platform and extensible region based on where you are most productive. Over the course of a design cycle, the base hardware and extensible regions can both evolve. A well-designed base platform can form the basis for multiple applications where Vitis tools extend the extensible region. You can export design content from Vivado to Vitis and vice versa.

Development teams can choose coupling that is as loose or as tight as appropriate. This approach promotes concurrent development and integration of the different elements comprising a heterogeneous system.