Synthesis tools do not optimize device library cells by default when they instantiate them. Even when instructed to optimize the device library cells, synthesis tools generally cannot perform the same level of optimization as with the RTL. Therefore, synthesis tools typically only perform optimizations on the paths to and from these cells but not through the cells.
For example, instantiating an SRL as part of a long path can create a bottleneck. The SRL has a longer clock-to-out delay than a regular register. To preserve the area reduction provided by the SRL, create a SRL with one delay less than the required delay. This approach improves the clock-to-out timing characteristics. Implement the last stage in a regular flip-flop.