A simple way to control clocking resources is to use the CLOCK_BUFFER_TYPE synthesis constraint or attribute. Use synthesis constraints to perform the following:
- Prevent BUFG inference
- Replace a BUFG with an alternative clocking structure
- Specify a clock buffer where none exists
Using synthesis constraints allows this type of control without requiring any modification to the code.
Place attributes in either of the following locations:
- Directly in the HDL code, which allows them to persist in the code
- As constraints in the XDC file, which allows this control without any changes needed to the source HDL code