AMD recommends using synchronous resets if you need a reset. Synchronous resets have the following advantages over asynchronous resets:
- Synchronous resets can directly map to more resource elements in the device architecture.
- Asynchronous resets impact the maximum clock frequency of the general logic structures. All AMD device general-purpose registers can program the set/reset as either asynchronous or synchronous. It can seem like there is no penalty in using asynchronous resets. Using a global asynchronous reset does not increase the control sets. However, the need to route this reset signal to all register elements increases routing complexity.
- Asynchronous resets have a greater probability of corrupting memory contents of block RAMs, LUTRAMs, and SRLs during reset assertion. This is especially true for registers with asynchronous resets that drive the input pins of block RAMs, LUTRAMs, and SRLs.
- Synchronous resets offer more flexibility for control set remapping when higher density or fine tuned placement is needed. A synchronous reset can be remapped to the data path of the register if an incompatible reset is found in the more optimally placed slice. This can reduce routing resource utilization and increase placement density where needed to allow proper fitting and improved achievable clock frequency.
Following are additional considerations:
- The clock works as a filter for small reset glitches for synchronous resets. However, if these glitches occur near the active clock edge, the flip-flop can become metastable.
- Synchronous resets sometimes require stretching the pulse width. This ensures the reset signal pulse is wide enough. The reset must be present during an active edge of the clock.
- When using asynchronous resets, remember to synchronize the
deassertion of the asynchronous reset. Although the relative timing between clock
and reset can be ignored during reset assertion, the reset release must be
synchronized to the clock. Avoiding the reset release edge synchronization can lead
to metastability.
During reset release, setup and hold timing conditions must be satisfied for the reset pin relative to the clock pin of a register. There are setup and hold conditions for asynchronous reset, for example reset recovery and removal timing. A violation of these conditions can cause the flip-flop to become metastable. This metastability can cause design failure due to switching to an unknown state. This situation is similar to the violation of setup and hold conditions for the flip-flop data pin.