Super Logic Region (SLR) - Super Logic Region (SLR) - 2026.1 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2026-07-22
Version
2026.1 English

A super logic region (SLR) is a single device die slice contained in an SSI technology device. Each SLR contains a subset of device resources, such as CLBs, block RAMs, DSP tiles, and GTs, with a similar structure to non-SSI devices.

The design stacks multiple SLR components vertically and connects them through an interposer to create an SSI technology device. SLR0 is the bottom SLR. As they ascend vertically, subsequent SLR components receive incremental names.

For example, the XCVP1802 device includes four SLR components. The system names the bottom SLR is SLR0. It names the SLR directly above SLR0 as SLR1, the SLR directly above SLR1 is SLR2, and the top SLR is SLR3.

Note: The AMD tools clearly identify SLR components in the graphical user interface (GUI) and in reports.