Timing analysis modifies specific paths using timing exceptions. The timing engine assumes by default that setup analysis must time all paths with a single cycle requirement to cover the most pessimistic clocking scenario. For certain paths, this is not true. Following are a few examples:
- The lack of a fixed phase relationship between the clocks prevents safe timing of asynchronous CDC paths. Ignore them (Clock Groups, False Path), or apply a datapath delay constraint (Max Delay Datapath Only).
- The sequential cells do not activate launch and capture edges at every clock cycle. Therefore, you relax the path requirement accordingly (Multicycle Path).
- The path delay requirement needs to be tightened to increase the design margin in hardware (Max Delay).
- A path through a combinatorial cell is static and does not need to be timed (False Path, Case Analysis).
- Perform the analysis using only a specific clock driven by a multiplexer (Case Analysis).
Use timing exceptions carefully. Do not add them to hide real timing problems.