Simulating a design with the Modular NoC and XPM NMUs/NSUs is the same as
simulating a design using the AXI NoC IP. You instantiate the AXI NoC IP in a Block
Design. After validate_noc executes, the tool merges
Modular NoC connectivity and constraints with the AXI NoC IP data from the Block Design.
The simulation flow then proceeds.
Even if validate_noc is not called
explicitly by you, it is called automatically when simulation is launched or exported in
Vivado. A new block named xlnoc.bd encompasses the collection of connection
components. These components include NPSs and NIDBs, which are necessary for
implementing the NoC routing solution.
When you run launch_simulation, the tool
creates the new xlnoc.bd block and a <design>_wrapper_sim_wrapper.v top-level wrapper
file to stitch the xlnoc block into the simulation. The original
<design>_wrapper is not modified but is
instantiated in the new top-level wrapper along with a single instance of the
constructed xlnoc.
To create the wrapper without launching the Vivado simulator, you can use the option launch_simulation -scripts_only. When the simulation is launched, the tool
internally executes the validate_noc command. Ensure
that you generate the output products for the BDs and IPs in the design before launching
the simulation.
Below is a code snippet before generating the scripts for launching simulation where you only have the original top-level wrapper under simulation.
When the simulation scripts are generated using the launch_simulation
–scripts_only command, the tool adds the xlnox.bd and
the <design>_wrapper_sim_wrapper.v file under the simulation
sources.
For information on the NoC simulation, refer to the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).
For Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2, refer to the following documents: