Simulating Modular NoC Design - 2024.2 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2024-12-18
Version
2024.2 English

Simulating a design using the Modular NoC that has XPM NMUs/NSUs is the same as simulating a design using the AXI NoC IP instantiated in a Block Design. Once validate_noc is executed, the Modular NoC connectivity and constraints are merged with the AXI NoC IP connectivity and constraints from the Block Design and the simulation flow proceeds. Even if validate_noc is not called explicitly by the user, it is called automatically when simulation is launched or exported in Vivado. A new block named xlnoc.bd is built to encompass the collection of connection components, such as NPSs and NIDBs, that are necessary for implementing the NoC routing solution.

When launching simulation using the launch_simulation command the tool creates the new block xlnoc.bd and a new top-level wrapper file named <design>_wrapper_sim_wrapper.v to stitch the xlnoc block into the simulation. The original <design>_wrapper is not modified but is instantiated in the new top-level wrapper along with a single instance of the constructed xlnoc. To create the wrapper without launching the Vivado simulator, you can use the option launch_simulation -scripts_only. When the simulation is launched, the tool internally executes the validate_noc command so you need to ensure that the output products are generated for the BDs and IPs in the design prior to launching the simulation.

Below is a code snippet prior to generating the scripts for launching simulation where you only have the original top-level wrapper under simulation.

Figure 1. Source Window Prior launch_simulation

When the simulation scripts are generated using the launch_simulation –scripts_only command, the tool adds the xlnox.bd and the <design>_wrapper_sim_wrapper.v file under the simulation sources.

Figure 2. Source Window After launch_simulation

For more information on the NoC simulation, see the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).