The following example utilization report is for a XCVP1802 Versal multi-SLR design. The report shows that the overall block RAM utilization is 15.06% with 32% in SLR3 and 3% in SLR1. In this case, the block RAM utilization by SLR is not evenly matched. If the utilization and imbalance increase further, this can require additional floorplanning.
AMD recommends assigning block RAM and DSP groups to SLR Pblocks to minimize SLR crossings of shared signals. For example, an address bus that fans out to a group of block RAMs spread across multiple SLRs can make timing closure harder. SLR crossings add delay to timing critical signals.
Device resource location or user I/O selection anchors IP to SLRs. Examples include GT, ILKN, PCIe, MRMAC, and DCMAC dedicated blocks, or memory interface controllers. AMD recommends the following:
- Pay special attention to dedicated block location and pinout selection to avoid data flow crossing SLR boundaries multiple times.
- Keep tightly interconnected modules and IP within the same SLR. If that is not possible, you can add pipeline registers. This allows the placer more flexibility to find a good solution despite the SLR crossing between logic groups.
- Keep critical logic within the same SLR. Ensure that main modules are properly pipelined at their interfaces. This increases the likelihood that placer can find SLR partitions with flip-flop to flip-flop SLR crossings.