Synthesis takes in RTL and timing constraints and generates an optimized netlist that is functionally equivalent to the RTL. In general, the synthesis tool can take any legal RTL and create the logic for it. Synthesis requires realistic timing constraints.
Note: When you use Vivado IP integrator and
your IP in a BD file, the Vivado tools
automatically run synthesis during BD implementation.
For additional information about synthesis, refer to the following resources:
- Vivado Design Suite User Guide: Synthesis (UG901)
- Vivado Design Suite QuickTake Video: Design Flows Overview