Running Report Methodology - Running Report Methodology - 2026.1 English

Running Report Methodology - Running Report Methodology - 2026.1 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID

UG1387

Release Date

2026-07-22

Version

2026.1 English

The Vivado tools provide a Methodology Report that specifically checks for compliance with methodology. The tools run different checks depending on the stage of the design process:

RTL design: RTL lint-style checks
Synthesized and implemented designs: Netlist, constraints, and timing checks

In Project Mode, the tools automatically run Report Methodology during implementation (opt_design or route_design) by default. To run these checks manually, use either of the following methods:

At the Tcl prompt, open the design to be validated, and enter following Tcl command: report_methodology
To run these checks from the Vivado IDE, open the design to be validated, and select Reports > Report Methodology.

Recommended: To identify common design issues, run this report the first time you synthesize the design. Run this report again after significant module additions, constraint changes, or clocking circuit changes.

Note: AMDreviews and checks violations for AMD-supplied IP cores.

The Methodology window lists any violations, as shown in the following figure. Ensure you understand the specific methodology violation and its implications clearly. Determine why the violation does not negatively impact your design.

Important: Resolve all Critical Warnings and most Warnings to ensure good QoR, timing analysis accuracy, and reliable hardware stability. For details, refer to this link in the Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388). For methodology check violations that you can safely ignore, use the waiver mechanism to waive the violations. For details, refer to this link in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).

Note: The tool does not report methodology checks related to RAMB and DSP primitive optional pipelining (SYNTH-6, SYNTH-11, SYNTH-12 and SYNTH-13). This occurs when setup timing is greater than 1 ns on all input or output paths for the primitives.

Figure 1. Methodology Window

For more information on running Report Methodology, refer to the Vivado Design Suite User Guide: System-Level Design Entry (UG895). Also, refer to this link in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).