The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 12/17/2025 Version 2025.2 | |
| Navigating Content by Design Process | Added UG1788. |
| Design Planning Considerations for Dynamic Function eXchange | Added RM note. |
| Validate NoC DRCs | Added section. |
| Use Case Block When Priority Encoder Not Needed | Updated correct coding block. |
| Reset Guidelines for DFX Use Cases | Added section. |
| Clock Multiplexing | Added Evenly Distributed Latency figure. |
| 06/25/2025 Version 2025.1 | |
| General updates | Added PS Wizard, AM026, and PG406. |
| Design Planning for Key IP Blocks | Updated PS Wizard with opt_design description. |
| Design Planning Considerations for Segmented Configuration | Updated description. |
| Design Planning Considerations for Tandem Configuration | Updated description. |
| Design Creation with Block Designs | Updated note. |
| Creating a Hardware Platform for the Platform-Based Design Flow | Updated block diagram example. |
| Defining the Apertures for XPMs | Removed \ from code block. |
| Parameters in XPM NoC | Updated NOC_FABRIC description. |
| Clock Routing, Root, and Distribution | Updated naming of CLOCK_EXPANSION_WINDOW. |
| Using the GCLK_DESKEW Property on a Clock Net | Added USER_CLOCK_VTREE_TYPE description and UG1388 reference to calibrated deskew. |
| Using the CLOCK_LOW_FANOUT Constraint | Updated limit description and reordered sections. |
| Using the CLOCK_ROUTE_GUIDE Constraint | Added MBUFG output note. |
| XPIO Global Clock Buffer Clock Enable Timing | Added details on Safe Clock Startup and added HARDSYNC clock loss description. |
| I/O Planning Design Flows | Added information on X5IO. |